The present invention relates generally to a multi nodal computer system comprising a number of nodes on which chips of different types reside.
An example for such multi nodal computer system is described in U.S. Letters Patent No. 7,484,118 B2. This system comprises a clock chip per node, which is the gate for a service interface into the system. The service interface comprises a service element, which sends commands to the clock chip and the clock chip provides the status of the node to the service element. The clock chip controls only the chips residing on its node, and the chips are appropriate for sending a check stop request to the associated clock chip in case of a malfunction. Depending on the source of the check stop request, either a system check stop, a node check stop, or a chip check stop is then performed.
These check stops stop either all chips in the systems, or only some chips on the affected node. The stopping of the respective chips needs to be performed synchronously in order to be able to analyze the cause of the malfunction. The IBM Technical Bulletin publication entitled “Synchronous Start/Stop in a Multi Nodal System”, IPCOM0000161108D, (Jul. 12, 2002), describes also a method to synchronously start all chips in a multi nodal system, while the different chips are connected to different clock chips and each clock chip to a different node controller.
For multi nodal computer systems that do not have a clock chip per node, a solution is needed that can start and stop all chips on a node synchronously. This solution must also be able to start and stop the different units on chip at the same clock cycle.